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rev. 1.0 12/13 copyright ? 2013 by silicon laboratories SL28EB742 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SL28EB742 ep ro c lock ? g enerator for i ntel ? ck505 c ompliance features eproclock? programmable technology ?? compliant intel ck505 clock spec ?? low power push-pull type differential output buffers ?? integrated resistors on differential clocks ?? wireless friendly 3-bits slew rate control on single-ended clocks ?? differential cpu clocks with pin selectable frequency ?? 100 mhz differential src clocks ?? selectable differential sata or src clocks ?? 96 mhz differential dot clock ?? 48 mhz usb clock ?? selectable 12 or 48 mhz clock ?? 25 mhz ouput ?? buffered reference clock 14.318 mhz ?? 14.318 mhz crystal input or clock input ?? i 2 c support with readback capabilities ?? triangular spread spectrum profile for maximum electromagnetic interference (emi) reduction ?? industrial temperature: ?40 to 85 c ?? 3.3 v power supply ?? 56-pin qfn package selectable differential src or cpu clock cpu src sata dot96 48m 48m/ 12m 33m 25m 14.318m x2/x3 x4/x7 x0/x1 x1 x1/2 x1 x2 x1 x1 ?? > 4000 bits of configurations ?? can be configured through smbus or hard coded ?? custom frequency sets ?? differential skew control on true or compliment or both ?? differential duty cycle control on true or compliment or both ?? differential amplitude control ?? differential and single-ended slew rate control ?? program internal or external series resistor on single-ended clocks ?? program different spread profiles ?? program different spread modulation rate selectable differential src or cpu clock cpu src sata dot96 48m 48m/ 12m 33m 25m 14.318m x2/x3 x4/x7 x0/x1 x1 x1/2 x1 x2 x1 x1 patents pending ordering information: see page 39 pin assignments * internal 100k-ohm pull-up resistor ** internal 100k-ohm pull down resistor ckpwrgd/pd#
SL28EB742 2 rev. 1.0 description the SL28EB742 is a high-performance clock generator suppor ting intel cedarview platforms. the SL28EB742 is rated to support extended grade temperature. utilizing an inexpensive 14.318 mhz crystal, it is capable of supporting multiple frequencies from four plls. the cpu clo ck can support a frequency range from 83.33 to 166 mhz by configuration of two strap pins. with a combination of strap pins and an i 2 c interface, the device a llows maximum configurability. eproclock ? is the world?s first non-volatile programmable clock. the eproclock ? technology allows boa rd designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable ty pically through device and/or board redesigns . eproclock ? technology can be configured through smbus or hard coded. functional block diagram crystal/ clkin pll 1 (ssc) otp logic core vr pll 4 (non-ssc) pll 3 (non-ssc) divider divider divider sclk sdata ref [1:0] cpu pci clkpwrgd/ pd# cpu_stp# fs [ c:a] xin xout 48m pll 2 (non-ssc) divider src sata / src0 dot96 12 / 48m 25m pci/src_stp# clkreq[3:1] itp_en sel_sata sel_12_48
SL28EB742 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1. powerdown (pd #) clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2. powerdown (pd# ) assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3. powerdown (pd# ) deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4. cpu_stp# assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5. cpu_stp# deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6. pci/src_stp# assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7. pci/src_stp# deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. test and measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. single-ended clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2. differential clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1. frequency select pin fs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2. serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3. data protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. pin descriptions: 56-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
SL28EB742 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions (vdd = 3.3 v, t a =25c) parameter symbol test co ndition min typ max unit supply voltage (extended) vdd (industrial) 3.3 v 5% 3.13 3.3 3.46 v supply voltage (commercial) vdd (commercial) 3.3 v 10% 2.97 3.3 3.63 v table 2. dc electrical specifications parameter symbol test condition min max unit 3.3 v operating voltage vdd core 3.3 5% 3.135 3.465 v 3.3 v input high voltage (se) v ih 2.0 v dd + 0.3 v 3.3 v input low voltage (se) v il v ss ? 0.3 0.8 v input high voltage v ihi2c sdata, sclk 2.2 ? v input low voltage v ili2c sdata, sclk ? 1.0 v fs input high voltage v ih_fs 0.7 vdd+0. 3 v fs input low voltage v il_fs v ss ? 0.3 0.35 v input high leakage current i ih except internal pull-down resistors, 0 < v in < v dd ?5 ? a input low leakage current i il except internal pull-up resistors, 0 < v in < v dd ?5 ? ? a 3.3 v output high voltage (se) v oh i oh = ?1 ma 2.4 ? v 3.3 v output low voltage (se) v ol i ol = 1 ma ? 0.4 v high-impedance output current i oz ?10 10 ? a input pin capacitance c in 1.5 5 pf output pin capacitance c out 6pf pin inductance l in ?7nh power down current idd_ pd ?1ma dynamic supply current idd _3.3 v all outputs enabled. se clocks with 5? traces. differential clocks with 5? traces. loading per ck505 spec. ?115ma
SL28EB742 rev. 1.0 5 table 3. ac electrical specifications parameter symbol test condition min max unit long-term accuracy l acc measured at vdd/2 differential ? 250 ppm clock input clkin duty cycle t dc measured at vdd/2 47 53 % clkin rise and fall times t r /t f measured between 0.2 v dd and 0.8 v dd 0.5 4.0 v/ns clkin cycle to cycle jitter t ccj measured at vdd/2 ? 250 ps clkin long term jitter t ltj measured at vdd/2 350 ps input high voltage v ih xin / clkin pin 2 vdd+0.3 v input low voltage v il xin / clkin pin ? 0.8 v input high current i ih xin / clkin pin, vin = vdd 35 a input low current i il xin / clkin pin, 0 < vin <0.8 ?35 ? a cpu at 0.7 v cpu duty cycle t dc measured at 0 v differential 45 55 % 83.33 mhz cpu period t period measured at 0 v differential at 0.1s 11.99880 12.00120 ns 83.33 mhz cpu period, ssc t periodss measured at 0 v differential at 0.1s 12.02887 2 12.03128 ns 83.33 mhz cpu absolute period t periodabs measured at 0 v differential at 1clock 11.18969 12.16344 ns 83.33 mhz cpu absolute period, ssc t periodssabs measured at 0 v differential at 1 clock 11.89687 12.16344 ns 100 mhz cpu period t period measured at 0 v differenti al at 0.1s 9.99900 10.0010 ns 100 mhz cpu period, ssc t periodss measured at 0 v differential at 0.1s 10.02406 10.02607 ns 100 mhz cpu absolute period t periodabs measured at 0 v differential at 1clock 9.87400 10.1260 ns 100 mhz cpu absolute period, ssc t periodssabs measured at 0 v differential at 1 clock 9.87406 10.1762 ns 133 mhz cpu period t period measured at 0 v differenti al at 0.1s 7.49925 7.50075 ns 133 mhz cpu period, ssc t periodss measured at 0 v differenti al at 0.1s 7.51804 7.51955 ns 133 mhz cpu absolute period t periodabs measured at 0 v differential at 1 clock 7.41425 7.58575 ns 133 mhz cpu absolute period, ssc t periodssabs measured at 0 v differential at 1 clock 7.41430 7.62340 ns
SL28EB742 6 rev. 1.0 166 mhz cpu period t period measured at 0 v differenti al at 0.1s 5.99940 6.00060 ns 166 mhz cpu period, ssc t periodss measured at 0 v differenti al at 0.1s 6.01444 6.01564 ns 166 mhz cpu absolute period t periodabs measured at 0 v differential at 1 clock 5.91440 6.08560 ns 166 mhz cpu absolute period, ssc t periodssabs measured at 0 v differential at 1 clock 5.91444 6.11572 ns cpu cycle to cycle jitter t ccj measured at 0 v differential ? 85 ps cpu cycle to cycle jitter for cpu 2 t ccj (cpu2) measured at 0 v differential ? 125 ps cpu0 to cpu1 skew skew measured at 0 v differential ? 100 ps long-term accuracy l acc measured at 0 v differential ? 100 ppm cpu rising/falling slew rate t r / t f measured differentially from 150 mv 2.5 8 v/ns rise/fall matching t rfm measured single-endedly from 75 mv ?20% voltage high v high 1.15 v voltage low v low ?0.3 ? v crossing point voltage at 0.7 v swing v ox 300 550 mv src at 0.7 v src duty cycle t dc measured at 0 v differential 45 55 % 100 mhz src period t period measured at 0 v differenti al at 0.1s 9.99900 10.0010 ns 100 mhz src period, ssc t periodss measured at 0 v differential at 0.1s 10.02406 10.02607 ns 100 mhz src absolute period t periodabs measured at 0 v differential at 1 clock 9.87400 10.1260 ns 100 mhz src absolute period, ssc t periodssabs measured at 0 v differential at 1 clock 9.87406 10.1762 ns any src clock skew from the earliest bank to the latest bank t skew(win- dow) measured at 0 v differential ? 3.0 ns src cycle to cycle jitter t ccj measured at 0 v differential ? 85 ps src long term accuracy l acc measured at 0 v differential ? 100 ppm src rising/falling slew rate t r / t f measured differentially from 150 mv 2.5 8 v/ns table 3. ac electrical specifications (continued) parameter symbol test condition min max unit
SL28EB742 rev. 1.0 7 rise/fall m-atching t rfm measured single-endedly from 75 mv ?20% voltage high v high 1.15 v voltage low v low ?0.3 ? v crossing point voltage at 0.7 v swing v ox 300 550 mv dot96 at 0.7 v dot96 duty cycle t dc measured at 0 v differential 45 55 % dot96 period t period measured at 0 v differential at 0.1s 10.4156 10.4177 ns dot96 absolute period t periodabs measured at 0 v differential at 0.1s 10.1656 10.6677 ns dot96 cycle to cycle jitter t ccj measured at 0 v differential at 1 clock ?250ps dot96 long term accuracy l acc measured at 0v differential at 1 clock ? 100 ppm dot96 rising/falling slew rate t r / t f measured differentially from 150 mv 2.5 8 v/ns rise/fall matching t rfm measured single-endedly from 75 mv ?20% voltage high v high 1.15 v voltage low v low ?0.3 ? v crossing point voltage at 0.7 v swing v ox 300 550 mv sata at 0.7 v satam duty cycle t dc measured at 0v differential 45 55 % sata cycle to cycle jitter t ccj measured at 0v differential at 1 clock ?125ps sata long term accuracy l acc measured at 0v differential at 1 clock ? 100 ppm sata rising/falling slew rate t r / t f measured differentially from 150 mv 2.5 8 v/ns rise/fall matching t rfm measured single-endedly from 75 mv ?20% voltage high v high 1.15 v voltage low v low ?0.3 ? v table 3. ac electrical specifications (continued) parameter symbol test condition min max unit
SL28EB742 8 rev. 1.0 crossing point voltage at 0.7 v swing v ox 300 550 mv pci/pcif at 3.3 v pci duty cycle t dc measurement at 1.5 v 45 55 % spread disabled pcif/pci period t period measurement at 1.5 v 29.99700 30.00300 ns spread enabled pcif/pci period t periodss measurement at 1.5 v 30.08421 30.23459 ns spread disabled pcif/pci period t periodabs measurement at 1.5 v 29.49700 30.50300 ns spread enabled pcif/pci period t periodssabs measurement at 1.5 v 29.56617 30.58421 ns spread enabled pcif and pci high time t high measurement at 2 v 12.27095 16.27995 ns spread enabled pcif and pci low time t low measurement at 0.8 v 11.87095 16.07995 ns spread disabled pcif and pci high time t high measurement at 2.0 v 12.27365 16.27665 ns spread disabled pcif and pci low time t low measurement at 0.8 v 11.87365 16.07665 ns pcif/pci rising/falling slew rate t r / t f measured between 0.8 v and 2.0 v 1.0 4.0 v/ns any pci clock to any pci clock skew t skew measurement at 1.5 v ? 1000 ps pcif and pci cycle to cycle jitter t ccj measurement at 1.5 v ? 300 ps pcif/pci long term accuracy l acc measurement at 1.5 v ? 100 ppm 48m, 12_48m at 3.3 v duty cycle t dc measurement at 1.5 v 45 55 % 48 mhz period t period measurement at 1.5 v 20.83125 20.83542 ns 48 mhz absolute period t periodabs measurement at 1.5 v 20.48125 21.18542 ns 48 mhz high time t high measurement at 2 v 8.216563 11.15198 ns 48 mhz low time t low measurement at 0.8 v 7.816563 10.95198 ns rising and falling edge rate t r / t f (48m) measured between 0.8 v and 2.0 v 1.0 2.0 v/ns rising and falling edge rate t r / t f (12_48m) measured between 0.8 v and 2.0 v 1.0 2.0 v/ns cycle to cycle jitter t ccj measurement at 1.5 v ? 300 ps table 3. ac electrical specifications (continued) parameter symbol test condition min max unit
SL28EB742 rev. 1.0 9 48m long term accuracy l acc measurement at 1.5 v ? 100 ppm 25m at 3.3 v duty cycle t dc measurement at 1.5 v 45 55 % period t period measurement at 1.5 v 39.996 40.004 ns absolute period t periodabs measurement at 1.5 v 39.32360 40.67640 ns rising and falling edge rate t r / t f measured between 0.8 v and 2.0 v 1.0 4.0 v/ns cycle to cycle jitter t ccj measurement at 1.5 v ? 300 ps 25m long term accuracy l acc measured at 1.5 v ? 100 ppm 14.318m, at 3.3 v duty cycle t dc measurement at 1.5 v 45 55 % period t period measurement at 1.5 v 69.82033 69.86224 ns absolute period t periodabs measurement at 1.5 v 68.83429 70.84826 ns high time t high measurement at 2 v 29.97543 38.46654 ns low time t low measurement at 0.8 v 29.57543 38.26654 ns rising and falling edge rate t r / t f measured between 0.8 v and 2.0 v 1.0 4.0 v/ns cycle to cycle jitter t ccj measurement at 1.5 v ? 500 ps long term accuracy l acc measurement at 1.5 v ? 100 ppm enable/disable and set-up clock stabilization from powerup t stable ?1.8ms stop clock set-up time t ss 10.0 ? ns table 3. ac electrical specifications (continued) parameter symbol test condition min max unit
SL28EB742 10 rev. 1.0 table 4. thermal conditions parameter symbol condition min max unit temperature, storage t s non-functional ?65 150 c temperature, operating ambient, extended t a functional ?40 85 c temperature, operating ambient, commercial t a functional 0 70 c temperature, junction t j functional ? 150 c dissipation, junction to case ? jc jedec (jesd 51) ? 20 c/w dissipation, junction to ambient ? ja jedec (jesd 51) ? 60 c/w note: for multiple supplies, the voltage on any input or i/o pin cannot exceed the power pin during powerup. power supply sequencing is not required. table 5. absolute maximum conditions parameter symbol test condition min max unit main supply voltage v dd_3.3 v functional ? 4.6 v input voltage v in relative to v ss ?0.5 4.6 v dc temperature, storage t s non-functional ?65 150 c temperature, operating ambient t a functional ?40 85 c temperature, junction t j functional ? 150 c dissipation, junction to case ? jc jedec (jesd 51) ? 20 c/ w dissipation, junction to ambient ? ja jedec (jesd 51) ? 60 c/ w esd protection (human body model) esd hbm jedec (jesd 22 - a114) 2000 ? v flammability rating ul-94 ul (class) v?0 moisture sensitivity level msl jedec (j-std-020) 1 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequenc- ing is not required.
SL28EB742 rev. 1.0 11 2. functional description 2.1. powerdown (pd#) clarification the ckpwrgd/pd# pin is a dual-funct ion pin. during initial powerup, th e pin functions as ckpwrgd. once ckpwrgd has been sampled high by the clock chip, th e pin assumes pd# functionality. the pd# pin is an asynchronous active low input used to shut off all clocks cleanly before shutting off power to the device. this signal is synchronized internally to the devic e before powering down the clock synthesizer. pd# is also an asynchronous input for powering up the system. when pd# is asserted low, clocks are driven to a low value and held before turning off the vcos and the crystal oscillator. 2.2. powerdown (pd#) assertion when pd# is sampled low by two consecutive rising edge s of cpuc, all single-ended outputs clocks will be held low on their next high-to-low transiti on and differential clocks will be held low. when powerdow n mode is desired as the initial power on state, pd# must be asserted low in less than 10 s after asserting ckpwrgd. . table 6. output driver status during cpu_stp and pcis_stp# cpu_stp# asserted pci_stp# asserted clkreq# asserted smbus oe disabled single-ended clocks stoppable running driven low running driven low non-stoppable running running running differential clocks stoppable clock driven high clo ck driven high clock driven low clock driven low clock driven low clock driven low clock driven low non-stoppable running running running table 7. output driver status all single-ended clocks a ll differential clocks w/o strap w/ strap clock clock# pd# = 0 (powerdown) low hi-z low low
SL28EB742 12 rev. 1.0 2.3. powerdown (pd#) deassertion the powerup latency is less th an 1.8 ms. this is the time from the deassertion of the pd# pin or the ramping of the power supply until the time that stable clocks are generated from the clock ch ip. all differential outputs stopped in a three-state condition resulting from powerdown are driven high in less than 300 s of pd# deassertion to a voltage greater than 200 mv. after the clock chip?s internal pll is powered up and locked, all outputs are enabled within a few clock cycles. figure 2 is an example showin g the relationship of clocks coming up. figure 1. powerdown assertion timing waveform figure 2. powerdown deassertion timing waveform pd usb, 48mhz dot96t dot96c srct 100mhz srcc 100mhz cput, 133mhz pci, 33 mhz ref cpuc, 133mhz dot96c pd cpuc, 133mhz cput, 133mhz srcc 100mhz usb, 48mhz dot96t srct 100mhz tstable <1.8 ms pci, 33mhz ref tdrive_pwrdn <300 ? s, >200 mv
SL28EB742 rev. 1.0 13 figure 3. ckpwrgd timing diagram fs_a, fs_b,fs_c ckpwrgd pwrgd_vrm vdd clock gen clock state clock outputs clock vco 0.2-0.3 ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd is ignored
SL28EB742 14 rev. 1.0 2.4. cpu_stp# assertion the cpu_stp# signal is an active low input used for synchronous stopping and starting the cpu output clocks while the rest of the clock generator continues to func tion. when the cpu_stp# pin is asserted, all cpu outputs that are set with the i 2 c configuration to be stoppable are stopped wit hin two to six cpu clock periods after being sampled by two rising edges of the internal cpuc cloc k. the final states of th e stopped cpu signals are cput = high and cpuc = low. 2.5. cpu_stp# deassertion the deassertion of the cpu_stp# signal causes all st opped cpu outputs to resume normal operation in a synchronous manner. no short or stretched clock puls es are produced when the cl ock resumes. the maximum latency from the deassertion to active outp uts is no more than two cpu clock cycles. figure 4. cpu_stp# assertion waveform figure 5. cpu_stp# deassertion waveform cpu_stp cput cpuc cpu_stp cput cpuc cput internal tdrive_cpu_stp, 10 ns>200 mv cpuc internal
SL28EB742 rev. 1.0 15 2.6. pci/src_stp# assertion the pci/src_stp# signal is an active low input used fo r synchronously stopping an d starting the pci outputs while the rest of the clock generator continues to functi on. the set-up time for capturing pci/src_stp# going low is 10 ns (t su ) (refer to figure 6). the pcif and src clocks are affected by the pci/src pin if their corresponding control bit in the i 2 c register is set to allow them to be free running. for src clocks assertion description, refer to the cpu_stp# descriptions in section 2.4 and section 2.5. figure 6. pci/src_stp# assertion waveform 2.7. pci/src_stp# deassertion the deassertion of the pci/src_stp# signal causes a ll pci and stoppable pcif to resume running in a synchronous manner within two pci clock periods and afte r pci/src_stp# transitions to a high level. similarly, pci/src_stp# deassertion will cause stoppable src cloc ks to resume running. for an src clocks deassertion description, refer to th e cpu_stp# description section 2.4 and section 2.5. figure 7. pci/src_stp# deassertion waveform
SL28EB742 16 rev. 1.0 3. test and measurement setup 3.1. single-ended clocks figure 8 shows the test load configuratio n for single-ended cl ock output signals. figure 8. single-ended clocks single load configuration figure 9. single-ended output signals (for ac parameters measurement)
SL28EB742 rev. 1.0 17 3.2. differential clock signals figure 10 shows the test load configuration for differential clock signals. figure 10. 0.7 v differential load configuration figure 11. differential measurement for differential output signals (for ac parameters measurement)
SL28EB742 18 rev. 1.0 figure 12. single-ended measurement for differential output signals (for ac parameters measurement)
SL28EB742 rev. 1.0 19 4. control registers 4.1. frequency select pin fs apply the appropriate logic levels to fs inputs before ckpwrgd assertion to achieve host clock frequency selection. when the clock chip sampled high on ckpw rgd and indicates that vtt voltage is stable then fs input values are sampled. this process employs a one -shot functionality and once the ckpwrgd sampled a valid high, all other fs, and ckpwrgd transitions are ignored except in test mode. table 8. frequency select pin (fs) sel_sata fsc fsb fsa cpu src sata pci 0 0 0 0 100.00 100.00 100.00 33.33 0 0 0 1 100.00 100.00 100.00 33.33 0 0 1 0 83.33 100.00 100.00 33.33 0 0 1 1 83.33 100.00 100.00 33.33 0 1 0 0 133.33 100.00 100.00 33.33 0 1 0 1 133.33 100.00 100.00 33.33 0 1 1 0 166.67 100.00 100.00 33.33 0 1 1 1 166.67 100.00 100.00 33.33 1 0 0 0 100.00 100.00 100.00 33.33 1 0 0 1 100.00 100.00 100.00 33.33 1 0 1 0 83.33 100.00 100.00 33.33 1 0 1 1 83.33 100.00 100.00 33.33 1 1 0 0 133.33 100.00 100.00 33.33 1 1 0 1 133.33 100.00 100.00 33.33 1 1 1 0 166.67 100.00 100.00 33.33 1 1 1 1 166.67 100.00 100.00 33.33
SL28EB742 20 rev. 1.0 4.2. serial data interface to enhance the flexibility and function of the clock synthe sizer, a two-signal serial interface is provided. through the serial data interface, various devi ce functions, such as individual clo ck output buffers are individually enabled or disabled. the registers associated with the serial data interface initializ e to their default setting at power-up. the use of this interface is optional. clock device register changes are normally made at system initialization, if any are required. the interface can not be used during system operation for power mana gement functions. 4.3. data protocol the clock driver serial protocol accepts byte write, by te read, block write, and block read operations from the controller. for block write/read operation, access the by tes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any comp lete byte is transferred. for byte write and byte read operations, the system controller can acce ss individually indexed bytes. the of fset of the indexed byte is encoded in the command code described in table 9. the block write and block read protocol is outlined in table 10 while table 11 outlines byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 9. command code definition bit description 7 0 = block read or block write operation; 1 = byte read or byte write operation. (6:0) byte offset for byte read or byte write operation. for block read or block wr ite operations, these bits should be '0000000'. table 10. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address?7 bits 8:2 slave address?7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count?8 bits 20 repeat start 28 acknowledge from slave 27:21 slave address?7 bits 36:29 data byte 1?8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2?8 bits 37:30 byte count from slave?8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave?8 bits
SL28EB742 rev. 1.0 21 .... data byte n?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave?8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave?8 bits .... not acknowledge .... stop table 11. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address?7 bits 8:2 slave address?7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte?8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address?7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave?8 bits 38 not acknowledge 39 stop table 10. block read and block write protocol (continued) block write protocol block read protocol bit description bit description
SL28EB742 22 rev. 1.0 reset settings = 000x0xxx control register 0. byte 0 bitd7d6d5d4d3d2d1d0 name spread enable sel_sata fsc fsb fsa type r/w r/w r/w r r/w r r r bit name function 7:6 reserved 5 spread enable enable spread for cpu/src/pci outputs 0=disable, 1=?0.5% 4 sel_sata see table 9 for sata/src selection. 3 reserved 2 fsc see table 9 for cpu frequency selection table. 1 fsb 0 fsa
SL28EB742 rev. 1.0 23 reset settings = 1111110 register 1. byte 1 bitd7d6d5d4d3d2d1d0 name dot96_ oe sata/ src0_oe cpu2/ src6_oe src2 src1 wol_en type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 dot96_oe output enable for dot96. 0 = output disabled, 1 = output enabled 6 sata/src0_oe output enable for sata/src0. 0 = output disabled, 1 = output enabled 5 cpu2/src6_oe output enable for cpu2/src6. 0 = output disabled, 1 = output enabled 4 src2 output enable for src2. 0 = output disabled, 1 = output enabled 3 src1 output enable for src1. 0 = output disabled, 1 = output enabled 2 reserved 1wol_en wake-on-lan enable bit. 25 mhz free running during vdd suspend (s-s tates). if this bit is set to 0, the xtal osc will also be powered down in the suspend states ) 0 reserved
SL28EB742 24 rev. 1.0 reset settings = 10111110 register 2. byte 2 bitd7d6d5d4 d3 d2d1d0 name 48m_oe 25m_oe ref_oe 12_48m_oe pci0_oe pcif_oe type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 748m_oe output enable for 48m. 0: output disabled. 1: output enabled. 6 reserved 5 25m_oe output enable for 25m. 0 = output disabled, 1 = output enabled 4 ref_oe output enable for ref. 0 = output disabled, 1 = output enabled 3 12_48m_oe output enable for 12_48m. 0 = output disabled, 1 = output enabled 2 pci0_oe output enable for pci0. 0 = output disabled, 1 = output enabled 1 pcif_oe output enable for pcif. 0 = output disabled, 1 = output enabled 0 reserved
SL28EB742 rev. 1.0 25 reset settings = 1100000 register 3. byte 3 bitd7d6d5d4d3d2d1d0 name cpu1_oe cpu0_oe clkreq#_3 clkreq#_3 clkreq#_2 clkreq#_2 clkreq#_1 clkreq#_1 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7cpu1_oe output enable for cpu1. 0 = output disabled, 1 = output enabled 6cpu0_oe output enable for cpu0. 0 = output disabled, 1 = output enabled 5 clkreq#_3 clock request for src2. 0 = not controlled, 1 = controlled 4 clkreq#_3 clock request for src6 (does not apply to cpu clock). 0 = not controlled, 1 = controlled 3 clkreq#_2 clock request for src2. 0 = not controlled, 1 = controlled 2 clkreq#_2 clock request for sata75m/src0. 0 = not controlled, 1 = controlled 1 clkreq#_1 clock request for src1. 0 = not controlled, 1 = controlled 0 clkreq#_1 clock request for sata75m/src0. 0 = not controlled, 1 = controlled
SL28EB742 26 rev. 1.0 reset settings = 00x0x000 register 4. byte 4 bitd7d6d5d4d3d2d1d0 name cpu1 12_48m cpu2 itp_en cpu0 type r/w r/w r r/w r r/w r/w r/w bit name function 7 reserved 6cpu1 cpu1 free run control. 0 = free running, 1 = stoppable 5 12_48m selectable 12_48m status. 0=48m, 1=12m 4cpu2 cpu2 free run control. 0 = free running, 1 = stoppable 3itp_en selectable cpue_itp/ src6 status. 0 = src6, 1 = cpu2 2 reserved 1cpu0 cpu0 free run control. 0 = free running, 1 = stoppable 0 reserved
SL28EB742 rev. 1.0 27 reset settings = 00010000 reset settings = 01010101 control register 5. byte 5 bitd7d6d5 d4 d3 d2 d1 d0 name sata75/src0 src6 src2 src1 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:5 reserved 4 sata75/src0 sata75/src0 free run control. 0 = free running, 1 = stoppable 3src6 src6 free run control. 0 = free running, 1 = stoppable 2src2 src2 free run control. 0 = free running, 1 = stoppable 1src1 src1 free run control. 0 = free running, 1 = stoppable 0 reserved control register 6. byte 6 bitd7d6d5d4d3d2d1d0 name cpu_amp src_amp dot96_amp sata_amp type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:6 cpu_amp cpu amplitude adjustment. 00 = 700 mv, 01 = 800 mv, 10 = 900 mv, 11 = 1000 mv 5:4 src_amp src amplitude adjustment. 00 = 700 mv, 01 = 800 mv, 10 = 900 mv, 11 = 1000 mv 3:2 dot96_amp dot96 amplitude adjustment. 00 = 700 mv, 01 = 800 mv, 10 = 900 mv, 11 = 1000 mv 1:0 sata_amp sata75/src0 amplitude adjustment. 00 = 700 mv, 01 = 800 mv, 10 = 900 mv, 11 = 1000 mv
SL28EB742 28 rev. 1.0 reset settings = 00011000 control register 7. byte 7 bitd7d6d5d4d3d2d1d0 name rev code bit 3 rev code bit 2 rev code bit 1 rev code bit 0 vendor id bit 3 vendor id bit 2 vendor id bit 1 vendor id bit 0 type rrrrrrrr bit name function 7 rev code bit 3 revision code bit 3 6 rev code bit 2 revision code bit 2 5 rev code bit 1 revision code bit 1 4 rev code bit 0 revision code bit 0 3 vendor id bit 3 vendor id bit 3 2 vendor id bit 2 vendor id bit 2 1 vendor id bit 1 vendor id bit 1 0 vendor id bit 0 vendor id bit 0
SL28EB742 rev. 1.0 29 reset settings = 00001111 control register 8. byte 8 bitd7d6d5d4d3d2d1d0 name bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 bc7 byte count register for block read operation. the default value for byte count is 15. in order to read beyond byte 15, the user should change the byte count limit to or beyond the byte th at is desired to be read. 6bc6 5bc5 4bc4 3bc3 2bc2 1bc1 0bc0
SL28EB742 30 rev. 1.0 reset settings = 11100001 control register 9. byte 9 bitd7d6d5d4d3d2d1d0 name src5 src4 src3 src5 src4 src3 pci0 pcif type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7src5 output enable for src5. 0 = output disabled, 1 = output enabled 6src4 output enable for src4. 0 = output disabled, 1 = output enabled 5src3 output enable for src3. 0 = output disabled, 1 = output enabled 4src5 src5 free run control. 0 = free running, 1 = stoppable 3src4 src4 free run control. 0 = free running, 1 = stoppable 2src3 src3 free run control. 0 = free running, 1 = stoppable 1pci0 pci0 free run control. 0 = free running, 1 = stoppable 0pcif pcif free run control. 0 = free running, 1 = stoppable
SL28EB742 rev. 1.0 31 reset settings = 00000000 reset settings = 10110111 control register 10. byte 10 bitd7d6d5d4d3d2d1d0 name type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:0 reserved control register 11. byte 11 bitd7d6d5d4d3d2d1d0 name 14m_bit2 14m_bit1 14m_bit0 25m_bit2 25m_bit1 25m_bit0 12_48m_ bit2 12_48m_ bit0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 14m_bit2 drive strength control - bit[2:0] normal mode default ?101? wireless friendly mode default to ?111? ? 614m_bit1 514m_bit0 425m_bit2 325m_bit1 225m_bit0 1 12_48m_bit2 0 12_48m_bit0
SL28EB742 32 rev. 1.0 reset settings = 10110100 control register 12. byte 12 bitd7d6d5d4d3d2d1 d0 name 48m_bit2 48m_bit1 48m_bit0 pci0_bit 2 pci0_bit1 pci0_bit0 12_48m_bit1 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 48m_bit2 drive strength control - bit[2:0] normal mode default ?101? wireless friendly mode default to ?111? ? 648m_bit1 548m_bit0 4pci0_bit2 3pci0_bit1 2pci0_bit0 1 reserved 0 12_48m_bit1
SL28EB742 rev. 1.0 33 reset settings = 10100000 control register 13. byte 13 bitd7d6d5d4d3d2d1 d0 name pcif_bit2 pcif_bit1 pcif_b it0 wireless friendly mode type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7 pcif_bit2 drive strength control?bi t[2:0] normal mode default 101 wireless friendly mode default to ?111? ? 6pcif_bit1 5pcif_bit0 4:1 reserved 0 wireless friendly mode wireless friendly mode. 0 = disabled, default all single-ended clocks slew rate config bits to 101 1 = enabled, default all single-ended cloc ks slew rate config bits to 111
SL28EB742 34 rev. 1.0 reset settings = 10101000 control register 14. byte 14 bit d7 d6 d5 d4d3d2d1 d0 name otp_4 otp_3 otp_2 otp_1 otp_0 type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:5 reserved 4 otp_4 otp_id. identification for programmed device 3 otp_3 2 otp_2 1 otp_1 0 otp_0
SL28EB742 rev. 1.0 35 5. pin descriptions: 56-pin qfn ckpwrgd/pd#
SL28EB742 36 rev. 1.0 table 12. 56-qfn pin definitions pin # name type description 1 pcif/itp_en** i/o, se, pd 33 mhz free running clock output/3.3 v lvttl input to enable src6 or cpu2_itp (sampled on the ckpwrgd assertion). 0 = src6, 1 = cpu2 2 clkreq#3** i, pd 3.3 v clock request input (internal 100 k ?? pull-down) 3 12_48m / sel12_48 i/o, se pu 12/48 mhz clock output/3.3 v-tolerance input for 12 mhz or 48 mhz selection (sampled at ckpwrg d assertion) (internal 100 k ? pull-up). 0=48m, 1=12m 4 vdd_48 pwr 3.3 v power supply 5 48m/fsa** i/o pd fixed 48 mhz clock output/3.3 v-to lerant input for cpu frequency selection (internal 100 k ? pull-down). refer to table 2 for vil_fs and vih_fs specifications. 6 gnd_48 gnd ground. 7 gnd_48 gnd ground. 8 dot96 o, dif fixed true 96 mhz clock output. 9 dot96# o, dif fixed complement 96 mhz clock output. 10 fsb** i, pd 3.3 v-tolerant input for cpu frequency selection (internal 100 k ? pull- down). refer to table 2 for vil_fs and vih_fs specifications. 11 gnd_sata gnd ground. 12 sata/src0 o, dif 100 mhz true differential serial reference clock. 13 sata/src0# o, dif 100 mhz complement differential serial reference clock. 14 vdd_sata pwr 3.3 v power supply. 15 src1 o, dif 100 mhz true differential serial reference clock. 16 src1# o, dif 100 mhz complement differential serial reference clock. 17 src2 o, dif 100 mhz true differential serial reference clock. 18 src2# o, dif 100 mhz complement differential serial reference clock. 19 src3 o, dif 100 mhz true differential serial reference clock. 20 src3# o, dif 100 mhz complement differential serial reference clock. 21 gnd_src gnd ground. 22 vdd_src pwr 3.3 v power supply. 23 src4# o, dif 100 mhz true differential serial reference clock. 24 src4 o, dif 100 mhz complement diff erential serial reference clock. 25 src5# o, dif 100 mhz true differential serial reference clock.
SL28EB742 rev. 1.0 37 26 src5 o, dif 100 mhz complement diff erential serial reference clock. 27 gnd_src gnd ground. 28 vdd_src pwr 3.3 v power supply. 29 src6#/cpu2_itp# o, dif selectable complement ary differential cpu or src clock output. itp_en = 0 @ ckpwrgd assertion = src6 itp_en = 1 @ ckpwrgd assertion = cpu2 30 src6/cpu2_itp o, dif selectable true differential cpu or src clock output. itp_en = 0 @ ckpwrgd assertion = src6 itp_en = 1 @ ckpwrgd assertion = cpu2 31 cpu1# o, dif complement differential cpu clock output. 32 cpu1 o, dif true differential cpu clock output. 33 vdd_cpu pwr 3.3 v power supply. 34 cpu0# o, dif complement differential cpu clock output. 35 cpu0 o, dif true differential cpu clock output. 36 gnd_cpu gnd ground 37 sclk i smbus compatible sclock. 38 sdata i/o smbus compatible sdata. 39 cpu_stp#* i, pu 3.3 v-tolerant input for stopping cpu outputs (internal 100 k ? pull-up). 40 pci/src_stp#* i, pu 3.3 v-toler ant input for stopping pci and src outputs (internal 100 k ? pull-up). 41 xout o 14.318 mhz crystal output. floa t xout if using only clkin (clock input). 42 xin/clkin i 14.318 mhz crystal input or 3.3 v, 14.318 mhz clock input 43 gnd_ref gnd ground for ref clock and wol support. 44 gnd_ref gnd ground for ref clock and wol support. 45 ref o 14.318 mhz reference output clock. 46 vdd_ref pwr 3.3 v power supply for ref clock and power to support wol. 47 vdd_ref pwr 3.3 v power supply for ref clock and power to support wol. 48 ckpwrgd/pd# i 3.3 v lvttl input. this pin is a level sensitive strobe used to deter- mine when latch inputs are valid and are ready to be sampled. 49 vdd_25 pwr 3.3 v power supply. table 12. 56-qfn pin definitions (continued) pin # name type description
SL28EB742 38 rev. 1.0 50 25m/fsc** i/o, pd fixed 25 mhz clock output /3.3 v-tolerant input for cpu frequency selection (internal 100 k ? pull-up). refer to dc electrical specifica- tions table for vil_fs and vih_fs specifications. 51 gnd_25 gnd ground. 52 clkreq#1** i, pd 3.3 v clock request input (internal 100 k ? pull-down) 53 clkreq#2** i, pd 3.3 v clock request input (internal 100 k ? pull-down) 54 pci0/sel_sata** i/o, se pd 33 mhz clock output/3.3 v lvttl input to enable 100 mhz sata (internal 100 k ? pull-up). 0 = sata/src0 = src0 1 = sata/src0 = sata 55 gnd_pci gnd ground. 56 vdd_pci pwr 3.3 v power supply. table 12. 56-qfn pin definitions (continued) pin # name type description
SL28EB742 rev. 1.0 39 6. ordering guide part number package type product flow lead-free SL28EB742alc 56-pin qfn industrial, 0 to 70 ? c SL28EB742alct 56-pin qfn tape and reel industrial, 0 to 70 ? c SL28EB742ali 56-pin qfn industrial, ?40 to 85 ? c SL28EB742alit 56-pin qfn tape and reel industrial, ?40 to 85 ? c
SL28EB742 40 rev. 1.0 7. package outline figure 13 illustrates the packag e details for the SL28EB742. table 13 lists the values for the dimensions shown in the illustration. figure 13. 56-lead qfn package
SL28EB742 rev. 1.0 41 table 13. package diagram dimensions symbol millimeters min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.18 0.25 0.30 d8.00 bsc d2 5.80 5.90 6.00 e0.50 bsc e8.00 bsc e2 5.80 5.90 6.00 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. 4. this drawing conforms to the jedec solid state outline mo-220.
SL28EB742 42 rev. 1.0 d ocument c hange l ist revision 0.1 to revision 0.2 ?? correct the pin description. ?? remove 75 mhz description on pin description. ?? remove wol function description ?? correct otp code to 01000
SL28EB742 rev. 1.0 43 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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